The FE1.1s chip is a high-performance, low-power integrated circuit that enables a USB 2.0 HUB with four output ports and corresponding status LEDs. It requires a minimum number of external components, which are essentially a quartz for the clock that defines the speed of the downstream ports (device outputs). It is fully compatible with the Universal Serial Bus Revision 2.0 (USB 2.0) specification and supports, on the Host side (Upstream Facing Port) the maximum speed of USB 2.0 (480 MHz) and Full-Speed mode, while on the device side (4 downstream ports) it is High-Speed, Full-Speed and Low-Speed (12 MHz) compatible. It is also compatible with the Universal Charging Solution profile and USB Battery Charging Specification 1.1. The component integrates four USB 2.0 transceivers and pull-up resistors on the data lines (upstream is 1.5 kΩ and so is downstream).

• Package: SSOP-28_150mil
• Fully USB 2.0 compatible
• Supports High-Speed (480 MHz), Full-Speed (12 MHz) and Low-Speed (1.5 MHz) modes
• Built-in USB 2.0 transceivers 
• Built-in 5 V to 3.3 V and 1.8 V regulator
• Integrated Power-On-Reset circuit
• Built-in 12 MHz oscillators with feedback resistor
• Phase Lock Loop (PLL) 12 MHz to 480 MHz 
• Single Transaction Translator (STT)
• 4 USB ports
• Status LEDs for the 4 output ports